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Altera_Forum
Honored Contributor
Honored ContributorSlow DDR2 reading
Hello,
I'm implementing a FIFO using the DDR2 RAM in a 3C120 development board. Basically, I have two memory pointers, one for writing and one for reading, and I sequentially write 255 64-bit words and then sequentially read 255 64-bit words. The write process is quite fast (it tooks a total of 4.2us for the 255 words), but the read process is a lot slower, taking almost 14x times (a total of 58.4us). I'm not using bursts, but the addresses both during write and during read are sequentially incremented. In the read process, the waitrequest signal remains asserted 24 cycles, while in the write process it is asserted only in one cycle. Is this behaviour normal and expectable? Or I am doing something really wrong? Thanks! Regards, Javier11 Replies
Altera_ForumThat is was I was starting to suspect, that this is the normal behaviour, and that the best idea is to use bursts. I was trying to avoid it for simplicity, and due to the odd number of words... but well, I will have to read 256 words and ignore the last one (also not taking it into account to update the counters), or do burst readings except for the last words. Perhaps it is even better to also write a dummy word so all addresses are ever aligned to power of two boundaries.
Thank you very much to all for your help!
