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Altera_Forum's avatar
Altera_Forum
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14 years ago

Slow DDR2 reading

Hello, I'm implementing a FIFO using the DDR2 RAM in a 3C120 development board. Basically, I have two memory pointers, one for writing and one for reading, and I sequentially write 255 64-bit word...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Yes, but to a different slave interface, and currently it has no functionality implemented, only the signals are declared. Anyway, I will try to remove it completely and test again (I will only need it to check the amount of data stored). I've also just checked that the input and output on-chip FIFOs (that are dual clock ones) are driven by the same DDR2 controller sysclk