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Honored Contributor
Honored ContributorSlow DDR2 reading
Hello, I'm implementing a FIFO using the DDR2 RAM in a 3C120 development board. Basically, I have two memory pointers, one for writing and one for reading, and I sequentially write 255 64-bit word...
Altera_ForumHonored Contributor
Honored ContributorI will try to get some with signaltap. The memory controller is set to use 125MHz from a 50MHz clock, and the logic that manages the memory uses as its clock the sysclk output from the memory controller.
