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Altera_Forum
Honored Contributor
Honored ContributorSlow DDR2 reading
Hello, I'm implementing a FIFO using the DDR2 RAM in a 3C120 development board. Basically, I have two memory pointers, one for writing and one for reading, and I sequentially write 255 64-bit word...
Altera_ForumHonored Contributor
Honored ContributorThe waveform is damn hard to read, I strongly suggest signaltap.
Anyway, what's the frequency of the memory controller and the whole logic? I'd say it's different, so SOPC inserts a slow handshaking adapter between different speed data.
