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Honored Contributor
Honored ContributorSlow DDR2 reading
Hello, I'm implementing a FIFO using the DDR2 RAM in a 3C120 development board. Basically, I have two memory pointers, one for writing and one for reading, and I sequentially write 255 64-bit word...
Altera_ForumHonored Contributor
Honored ContributorHello,
The DDR2 controller is configured at full rate and full rate bridge, with local interface width 64-bit. It is only connected to one master, that checks from an on-chip FIFO if 255 64-bit words are available, and sequentially reads from it and increases the write address, and a data available counter. Then, it checks if there is enough room in an on-chip output FIFO for 255 words, and if so, and if the data available counter is 255 or more, reads 255 words and writes them to the output FIFO, and repeats the cycle. Instead of signal-tap captures, I've logic analyzer captures. One shows the complete write process, and the beginning of the read cycle, and the other the end of the write process and the start of the read process. The relevant signals are: D1(2): avalon read D1(3): avalon write D1(4): avalon waitrequest Regards, Javier
