Single Ended Clk to Differential clock

Hi,

I am working on Cyclone V SoC Development Kit, using the High Speed Mezanning Card (HSMC Board).

I have to respect the order of LVDS inputs, the LVDS input clock must be in the middle of incoming signals. I thought of using HSMA_CLK_IN_P1 and HSMA_CLK_IN_N1 of the HSMC Board but this pair cannot be connected get a LVDS value on the FPGA. I was wondering if I can use 9 signals of Bank 3 of the HSMC port with the clock in the middle... In other words, use any pair (HSMA_RX_D_PX,HSMA_RX_D_NX) and assign it to this differential clock.

Thanks in advance,