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sa_lahrich's avatar
sa_lahrich
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5 years ago
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Single Ended Clk to Differential clock

Hi, I am working on Cyclone V SoC Development Kit, using the High Speed Mezanning Card (HSMC Board). I have to respect the order of LVDS inputs, the LVDS input clock must be in the middle of in...
  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    5 years ago

    Hi Samah Lahrich

    Thanks for your inquiry.

    Can you help to guide me on the connection you wanted to work on, possibly with a simple diagram?

    Thanks.

    Eng Wei

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Samah Lahrich

Thanks for your inquiry.

Can you help to guide me on the connection you wanted to work on, possibly with a simple diagram?

Thanks.

Eng Wei

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Samah Lahrich

We do not receive any response from you to the previous question that we have asked. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei