Simulation of Cordic sincos IP core: Wrong signals for negative input signals

Question

Hi,

i have problems with the Cordic sincos IPcore (https://www.altera.com/en_US/pdfs/literature/ug/ug_cordic.pdf).

When i do the simulation, for positive signals i get the right signals but for negative input signals i receive wrong output signals and some of them are out of range. Am i doing a mistake?

Here is an example out of my simulation:

Input angle: 1110010010000111111011010100 (-3.14159265)

Output cosine: 001010011101010101001100000 (0,6523..)

Output sine: 110011111001000010001100001 (-1,242..)

Best regards

altera_forum · Answer

I just read through the core description (https://www.altera.com/en_us/pdfs/literature/ug/ug_cordic.pdf). I can't figure out why you'd ever create a cordic (http://zipcpu.com/dsp/2017/08/30/cordic.html) that would use radians for its angles, given the serious problems with radian units discussed here.http://zipcpu.com/dsp/2017/06/15/no-pi-for-you.html (http://zipcpu.com/dsp/2017/06/15/no-pi-for-you.html)

Does this core really use radians?

Dan

altera_forum · Answer

Hey Musti87,

i see the problem, you made a simple mistake. You have to learn how to convert a positive binary representation into two's complement form and reverse. Then you will see that the simulation works fine :cool:

altera_forum · Answer

To save us from guessing you should tell all sincos configuration parameters.

altera_forum · Answer

I solved the problem, i just made a beginner failure. My problem was that i didnt know how to depict a negativ binary representation right.

For example the input value above representing -pi is wrong, the right representation for -pi is: 1001101101111000000100101100 (1 sign bit, two integer bits, 25 fractional bits)

Therefore i wasn't able to evaluate the simulation right. So everything is working fine.

Forum Discussion

Simulation of Cordic sincos IP core: Wrong signals for negative input signals

4 Replies

Recent Discussions

Correct way to configure the RGMII input and output pins on a MAX10 FPGA

PCIe Enumeration Failure for CXL IP

Behavior of 10 GX Avalon-MM Interface for PCI Express* IP Core when byteenable=16'h0000

Regarding MIPI CSI 2 TX

How to Prevent Agilex 7 F-tile PMA Direct PHY TX Lane Skew