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Altera_Forum's avatar
Altera_Forum
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15 years ago

Simple VIP system produces incorrect output

Dear fellows, need your help...

System notation:

PG = Pattern Generator

CSC = Color Space Converter

CR = Chroma Resampler

CVI = Clocked Video Input

CVO = Clocked Video Output

"Busted" = No Vsync, Hsync is not continuous (gets interrupted looks like on a frame by frame basisi), Data Valid looks OK (inhibited during vertical blanknig I guess).

Video output with discrete syncs is present and correct when I build the following system (single clock domain) based on one SOPC block:

[External 74.25MHz clock -> PG (720p 4:4:4 RGB) -> CSC (RGB to YUV) -> CR (4:4:4 to 4:2:2) -> CR (4:2:2 to 4:4:4) -> CSC (YUV to RGB) -> CVO]

Video Output is "Busted" when I build the following system (single clock domain) based on 2 SOPC blocks:

Block 1:

[External 74.25MHz clock -> PG (720p 4:4:4 RGB) -> CVO]

connects to

Block 2:

[External 74.25MHz clock -> CVI -> CSC (RGB to YUV) -> CR (4:4:4 to 4:2:2) -> CR (4:2:2 to 4:4:4) -> CSC (YUV to RGB) -> CVO]

I have been at this for 5 days now. I usually resolve these myself - this one is tough.

I get underflow asserted by the CVO of Block 2 when the problem happens.

The system is stand-alone, i.e. no control from Avalon master.

Timing is met.

SDC files for CVI and CVO are included into compilation.

Undeflow pin of the resultant SOPC Block 2 stays asserted.

Locked input is connected to the system PLL output.

The PLL is fed from an external DVI interface, which is driven by an Astro Pattern generator producing 720p format (I am just using the clock for now).

Any suggestions are highly appreciated - I have not slept in days :)

Thanks to all.

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    Did you try to increase the size of the FIFOs for the CVI and CVO?

    Have you set "FIFO level at which to start output" to a value that is close to the FIFO size

    in the CVOs?

    Did you manage to get the simpler system working?

    Block 1:

    [External 74.25MHz clock -> PG (720p 4:4:4 RGB) -> CVO]

    connects to

    Block 2:

    [External 74.25MHz clock -> CVI -> CVO]
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    My input is 1280x720 (1650x750 with blanking), I tried CVI and CVO FIFOs of the size from 1280 to 4096 - did not help.

    The CVO threshold has been attempted at 500, 1000 and 4095 - did not help.

    Tried using dual clocks (74.25MHz at the CVI input and CVO output and 74.25*5/3 internaly for SOPC processing) - did not help.

    Yes, the simpler system using just a PG and CVO did work.

    It appears the system works as long as the VIP Pattern Generator is

    a) used as a source of video stream, and

    b) stays within the last SOPC block in the chain. If the PG is removed to a separate SOPC block (PG + CVO), followed by (CVI + whatever + CVO) block, then this immediately stops working properly with the symptoms descibed in the oroginal post as "Busted".

    Thanks for your suggestions - look forward to additional feedback.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi, I am not sure, but could this result by getting backpressure in the longer cain? The PG to CVO probably works, because the PG can stop and continue to deliver the patterns just as needed. I had some problems with porting a project from PG to a CVI because of that problem. If this is the case you will need extra framebuffer to get output, but I am not sure about that. Perhaps it is a clue, otherwise nevermind.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I really hope that having a frame buffer to perform a simple color space conversion and chroma resampling is not a requirement. The platform I am using has no frame buffering capabilities.

    Dear all, does anyone else beleive I must use a frame buffer to connect CVI + CVC + Chroma Resampler + CVO ?

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The problem has been resolved.

    To the benefit of all folks here I would like to report that Quartus II 9.1 SP1-based VIP was the root-cause of the problem

    Going back to Quartus II 9.0 SP2-based VIP resolved the problem.

    I simply re-built the design using the previous version of tools - no other changes. Now the image is getting through the entire processing chain.

    Thank you to everyone.