Simple Avalon-MM to onchip memory

Your master component is not monitoring the waitrequest input signal. All masters have to acknowledge waitrequest, keeping the read or write request on the interface until waitrequest goes high from the interconnect.

chipselect is an input for tri-state slaves, not an output for masters. Are you connecting to a tri-state conduit or other off-chip tri-state device?

Does your system successfully generate in Qsys/Platform Designer?

Have you checked the compilation report to verify that the .hex file is associated with and initializing the RAM properly?