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ALMSlinger's avatar
ALMSlinger
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2 years ago

Signaltap on dut|altpcie_a10_hip_pipen1b|test_out[319:0]

Hello, I am using pld_clk as signaltap clk to sample the test_out[319:0] signals of the pipe interface in Arria10GX HIP. But on the board the signaltap complains that pld_clk was not found. This h...
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ALMSlinger's avatar
ALMSlinger
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2 years ago

Wincent,

  1. The test_out signals are the pipe interface signals. I need to see what is coming out of the MAC/PCS sublayer.
  2. The test_out to coreclkout is across clock domains. You can see this from the timing analyzer report. Please see the picture.
  3. I do not have a picture of signaltap where it complained that the sampling clock was missing. But the screen shot of the signaltap screen is attached.
  4. Yes! LTSSM enters L0 state.

I have attached the Arria 10 GX dev board example design project with this signal tap. Please check the attached zip file.