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Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Nandish Jasani,

When you said it won't work - do you mean no return data back to RX or the RX return data is wrong value ?

I don't see your TSE IP setting screen shot. Can you re-attached the screen shot again ?

If you suspect is TSE IP internal FIFO issue, then

  • You can increase the FIFO depth to change it to 32 bits FIFO

Additional debug suggestion to you is

  • You can also disable the TSE MAC internal loopback setting to see if TSE output data to PHY side to isolate it's loopback setting issue or TX data traffic transaction issue
  • Pls signal_tap both Avalon ST Tx transaction and Avalon ST Rx transaction. I expect there will be back pressure status signal from TSE internal FIFO or error signal status explaining why it's failing at your test run

Thanks.

Regards,

dlim

NJasa's avatar
NJasa
Icon for New Contributor rankNew Contributor
5 years ago

Hey Thanks for your reply and sorry for late reply. I have attached TSE IP Qsys settings.

I had tried 32 bits FIFO, but still problem persist. Actually in my code i am checking TX and Rx status counters. So following is problem i found.

1) Sometimes TX OK Counter increments but TXOctet transmit value shows less and random from my set value of 1514 bytes. If transmit frame is ok then why its shows TX Octet transmitted value less.

2) Same frame is received success fully with RXoctetreceived byte is equal to Tx octet byte transmitted. But sometimes rxframecheckerror shows, as this is internal loopback then why framecheck error shows?

3) Recevied frame is also wrong from what i transmitted. All bytes are shows wrong including MAC Destination and Source address.

I think you are right, there is something problem with internal FIFO.

I will try what you suggest. And also check my TSE IP setting, if something wrong, please suggest to correct it. Have you check my C code? is there any thing wrong in it?

Thanks

Nandish Jasani.