Seriallite III

My apologies for the delayed response, did not notice you have further questions. Actually, its hard to distringuish which PCS blocks are implemented partially in the core and hard PCS. Example, the block synchronizer is using the hard PCS but has some control in the core logic to ensure it meets the synchronization requirements.

You can instead look at the hard PCS instead to understand what are the blocks implemented in hard PCS. Please refer to our user guide; look for how the hard PCS blocks are used in Interlaken mode. (The PCS configuration for Serial Lite II and Interlaken are approximately similar).

SerialLite III user guide:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_slite3_streaming.pdf

Arria 10 Phy User Guie (refer to Pg 94).

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

Regards,

Nathan