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host's avatar
host
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Serial Lite III "start_of_burst" and "end_of_burst"

I'm using the Serial Lite III IP in duplex mode on a Stratix 10 FPGA. In the Tx direction the IP has the following user driven input signals: start_of_burst_tx end_of_burst_tx My mode of work req...
Transceiver
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,


I’m glad that your design is working now, I now transition this thread to community support. If you have a new question. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you,

Kshitij Goel