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host's avatar
host
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Serial Lite III "start_of_burst" and "end_of_burst"

I'm using the Serial Lite III IP in duplex mode on a Stratix 10 FPGA. In the Tx direction the IP has the following user driven input signals: start_of_burst_tx end_of_burst_tx My mode of work req...
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Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


It means you are using the continuous mode, in that case it is dependent on valid, valid should be continuously high. For the example waveform please refer 5.8. User Data Interface Waveforms (intel.com) Figure 13.


As continuous mode is one long burst, in this mode the "start_of_burst" signal is asserted only once at the start of the data. And you can optionally send an end of burst signal at the end of continuous mode.


Refer 5.9.2. Signals for Intel® Stratix® 10 Devices for more info.


Thank you,

Kshitij Goel