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host's avatar
host
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Serial Lite III "start_of_burst" and "end_of_burst"

I'm using the Serial Lite III IP in duplex mode on a Stratix 10 FPGA. In the Tx direction the IP has the following user driven input signals: start_of_burst_tx end_of_burst_tx My mode of work req...
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host's avatar
host
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

You say:

Not EVERY TIME, I assume you are having continuous data or you are sending data in burst form, so you have to assert the "end of burst" signal one-time at the end.

But my data doesn't have an "end"
It's an endless stream of data that starts when the FPGA is powered on and NEVER seizes.

When would you assert "end of burst" in that case ?