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host's avatar
host
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Serial Lite III "start_of_burst" and "end_of_burst"

I'm using the Serial Lite III IP in duplex mode on a Stratix 10 FPGA. In the Tx direction the IP has the following user driven input signals: start_of_burst_tx end_of_burst_tx My mode of work req...
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Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


If my data isn't really segmented into packets, do I have to assert the "end of burst" signal EVERY TIME that I de-assert valid ?

[KG] - Not EVERY TIME, I assume you are having continuous data or you are sending data in burst form, so you have to assert the "end of burst" signal one-time at the end. See Figure 13 5.8. User Data Interface Waveforms (intel.com)


If I don't - doesn't this mean that I can simply tie it to GND?

[KG] - You cannot tie to GND.


Thank you,

Kshitij Goel