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Altera_Forum's avatar
Altera_Forum
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16 years ago

SERDES 6.25Gbps ALT2GXB rx_freqlocked

Hi All,

I have two Stratix II FPGAs (in two boards) communicating through 20 SERDES channels (Basic protocol). Usually things work fine. When one of the boards is not connected, I expect that the SERDES CDR will not lock (to data) and should give out rx_freqlocked LOW. Instead what I see is intermittently the CDR senses data (may be noise?? or crosstalk as 4 other SERDES links are active) and gives out rx_freqlocked as HIGH.

My question is, is there anyway I can use any output from the SERDES block to reliably sense that there is no connection and a valid signal? (by adjusting any parameters?). In PIPE mode there seems to be more control for signal detection. What about in Basic mode?

Protocol - Basic

I have enabled manual equalizer control

RXVcm = 0.85

Eq DC Gain = 1

Term Resisitor = 100 ohms

Thanks,

El

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I think, that checking for valid 8b_10b codes based on rx_syncstatus and rx_errdetect should give a more reliable link detection. But also a simple on-delay for rx_freqlocked may be sufficient to filter false link detection.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    I appreciate your immediate response. That was fast!!! Thanks.

    I have not enabled syncstatus signal when creating the block. I will do that and check if that solves the problem

    I did check rx_errdetect earlier and found that there was no error (on particular byte lanes).

    Regarding delaying rx_freqdetect, seems like it is stable and high for a very long time, even though it should not be receiving anything valid,

    But I do a digital reset (after few us delay)if I find that there is no rx_freqlocked.