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VenkateshSathar's avatar
VenkateshSathar
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

SDRAM Throughput problems using Arria 10 SOC

HI, I was doing a test on Arria 10 soc board regarding fsdram0 and fsdram1 bus speed test using msgdma but I am facing the problem as follows: For fpga fabric 100MHz clock I got a write speed of 8....
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Sorry, I still don't quite get your question here.

May I know are you changing your DDR3 IP operating frequency or DQ data width ?

  • If yes, then I would expect more BW transfer
  • If no, then I would expect the same BW transfer

My point is changing FPGA core clock frequency won't affect the BW transfer

Thanks.

Regards,

dlim

  • VenkateshSathar's avatar
    VenkateshSathar
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    May I know are you changing your DDR3 IP operating frequency or DQ data width ?

    • If yes, then I would expect more BW transfer
    • If no, then I would expect the same BW transfer

    --> for the above question also my answer is I changed my ddr3 operating frequency also from 600MHz to 750MHz still I am getting the same bandwidth or speed of transfer.

    My point is changing FPGA core clock frequency won't affect the BW transfer

    --> If we change or increase FPGA core clock frequency and supply more data then why not increase in the speed of data transfer because according to all the documents or datasheets shared by intel for burst mode atleast 60% efficiency i should suppose to get if I use everything upto the max. But I am getting hardly 30% efficiency only. May I know why or what factors affects this..?