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VenkateshSathar's avatar
VenkateshSathar
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

SDRAM Throughput problems using Arria 10 SOC

HI, I was doing a test on Arria 10 soc board regarding fsdram0 and fsdram1 bus speed test using msgdma but I am facing the problem as follows: For fpga fabric 100MHz clock I got a write speed of 8....
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

Sorry. I am confused on your calculation.

In theory, DDR3 or DDR4 BW can be calculated using below formula.

DDR3/DDR4 BW = operating freq (MHz) x 2 x DQ data width

From your diagram, I can see that the theoretical BW will be 1066MHz x 2 x 64 ~ 17GBps

Adjusting FPGA core clock frequency will only affect the speed where user transfer data to DDR3/DDR4 IP but it will not change the BW of the DDR3/DDR4 IP unless you change the operating frequency or DQ data width.

Thanks.

Regards,

dlim

  • VenkateshSathar's avatar
    VenkateshSathar
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Yeah I also mean that only when I changed Fpga core clock from 100MHz to 200MHz I should suppose to see double the rate of 8.88Gbps which I was getting previously why because DDR3 I have configured is for 600MHz for 32 DQ bits i.e.., 600MHz*2*32 = 37.5Gbps.

    Where as through fsdram0 bus when I connected for 100MHz also I see same 8.88Gbps and for 200MHz also I see same 8.88Gbps which is very strange.