SDRAM Controller

Ok. I have loaded the design into Quartus II Version 8 SE, and updated the database to work in my environment. I recompiled and verified the simulation in the Quartus simulator. I have confirmed that the simlation is a timing simulation, using an unconstrained project. The target shows as a Cyclone III, Is this correct? And the timing analyzer messages indicate a critical warning on an unconstrained file for optimization.

I would just like to take a moment as a side note to say that I totally agree with FVM in that the sense that I get is this method of simulation using a stimulus file instead of a written testbench does strike me as a potential problem spot. Did you make it or did you get it from some Altera source? I am just wondering because I generally have not had very much success with the Quartus simulator (just too limited using vectors). And I really am not certain that the back annotated delays are going to allow the operation of the RTL post fit. What I mean is...I have done simulations with the stimulus editor where I have improperly triggered logic at times when state-machines may not even care about things...For example trying to write lines during a refresh cycle or some other parrallel RTL event.

Long story Short.... Have you seen the Functional model simulate properly yet? Start there with a known good testbench, and a tool Like the Modelsim Simulator and then do the gate-timing.

Hope this helps, and as more information is available throughout the day(as I have time to work on it) I will post my findings.

Daniel Short