SDI video output not working in CvP mode

Thank you Chee Pin for your response and provide me detailed steps to debug the fPLL lock

Followed below steps so far :

1. Try web case (workaround/fix): changed the QSF assignment to change the reset control from the Avalon-MM register to the pll_powerdown input: This did not help and still no lock when I toggle the pll_powerdown input

2.Implement Avalon-MM register Interface : Enable the dynamic reconfiguration interface and enable control and status registers and add custom Avalon control interface IP to access the fPLL registers. Update the fPLL block and make appropriate port connection and build the project.

Please review below settings and ports:

3.Try to reset the fPLL by toggling to fPLL reset register i.e. 0x2E0[0] , no change is observed in pll_cal_busy and pll_locked signals

Just to make sure I am correctly accessing the fPLL registers, I read few registers and get some default values, can you confirm if these values are correct

system console commands

% ist::read_tcvr_pll_reg 0x0
0x00000002
% ist::read_tcvr_pll_reg 0x1
0x00000001
% ist::read_tcvr_pll_reg 0x2
0x00000000
% ist::read_tcvr_pll_reg 0x3
0x00000000

when I write '1' into 0x2E0 command and read back I get the correct value

% ist::write_tcvr_pll_reg 0x2E0 1

% ist::read_tcvr_pll_reg 0x2E0
0x00000001

when I write '0' into 0x2E0 command and read back I get the correct value

% ist::write_tcvr_pll_reg 0x2E0 0

% ist::read_tcvr_pll_reg 0x2E0
0x00000000

4. Next step is to try reconfigure the fPLL, Could you refer some documentation or steps for fPLL reconfiguration process ?

fPLL refclk and CLKUSR are directly sourced from stable and free-running oscillators on-board and they seems to be good because everything is working when CvP mode is disabled.

Regards,

Piyush.