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Piyush_Patel's avatar
Piyush_Patel
Icon for New Contributor rankNew Contributor
5 years ago
Solved

SDI video output not working in CvP mode

We are trying to leverage the arria 10 CvP (Configuration Via Protocol) feature into the current project. So far we have followed the steps as per user guide ug_a10_cvp_prop.pdf As part of the proc...
  • Piyush_Patel's avatar
    Piyush_Patel
    5 years ago

    Hi Chee pin and John

    I followed the steps mentioned in section 7.5.2. Fractional PLL Recalibration of ug_arria10_xcvr_phy.pdf

    I implemented the system console command sequence as below :

    # Follow these steps to re calibrate the fPLL:

    # Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0]
    #::ist::write_tcvr_pll_reg 0x000 2

    #Wait for reconfig_waitrequest to be deasserted (logic low) or wait until capability register of PreSICE Avalon memory-mapped interface control0x280[2]=0x0
    #::ist::read_tcvr_pll_reg 0x280

    #To calibrate the fPLL, Read-Modify-Write 0x1 to bit[1] of address 0x100 of the fPLL
    #::ist::write_tcvr_pll_reg 0x100 2

    #Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0]
    #::ist::write_tcvr_pll_reg 0x000 1

    I do get the fPLL lock and SDI output is up and running successfully.

    I really appreciate your suggestions

    Regards,

    Piyush,

    Regards,

    Piyush.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


I am Chee Pin and will be working together with John to assist you on this case. I will be focusing on the fPLL not lock perspective.


Please see my responses as following:


1. As I understand it, you mentioned that you have tried to perform a reset to the fPLL using the pll_powerdown input port. Not sure if you are aware of it, by default the A10 fPLL internal reset signal is controlled by AVMM register but not the pll_powerdown input port. You can refer to the following KDB for further details:


https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/hsio/2020/why-is-the-assertion-of-pllpowerdown-input-unable-to-reset-the-i.html


Can you try to reset the fPLL by writing to fPLL reset register ie 0x2E0[0] to see if there is any difference? You can monitor the pll_cal_busy and pll_locked after you writing to the reset register.


2. If the above is not working, you can try to perform a fPLL recalibration followed by reset to see if it helps.


3. Regarding your inquiry if the calibration has succeeded, you may check on the following:


i. In signaltap, after programming, you should observed pll_cal_busy high and then go low to indicate calibration has taken place


ii. Please ensure the fPLL refclk and CLKUSR are directly sourced from stable and free-running oscillators on-board. These signals need to be stable and free-running prior to device power up.


Please let me know if there is any concern. Thank you.


  • Piyush_Patel's avatar
    Piyush_Patel
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thank you Chee Pin for your response and provide me detailed steps to debug the fPLL lock

    Followed below steps so far :

    1. Try web case (workaround/fix): changed the QSF assignment to change the reset control from the Avalon-MM register to the pll_powerdown input: This did not help and still no lock when I toggle the pll_powerdown input

    2.Implement Avalon-MM register Interface : Enable the dynamic reconfiguration interface and enable control and status registers and add custom Avalon control interface IP to access the fPLL registers. Update the fPLL block and make appropriate port connection and build the project.

    Please review below settings and ports:

    3.Try to reset the fPLL by toggling to fPLL reset register i.e. 0x2E0[0] , no change is observed in pll_cal_busy and pll_locked signals

    Just to make sure I am correctly accessing the fPLL registers, I read few registers and get some default values, can you confirm if these values are correct

    system console commands

    % ist::read_tcvr_pll_reg 0x0
    0x00000002
    % ist::read_tcvr_pll_reg 0x1
    0x00000001
    % ist::read_tcvr_pll_reg 0x2
    0x00000000
    % ist::read_tcvr_pll_reg 0x3
    0x00000000

    when I write '1' into 0x2E0 command and read back I get the correct value

    % ist::write_tcvr_pll_reg 0x2E0 1

    % ist::read_tcvr_pll_reg 0x2E0
    0x00000001

    when I write '0' into 0x2E0 command and read back I get the correct value

    % ist::write_tcvr_pll_reg 0x2E0 0

    % ist::read_tcvr_pll_reg 0x2E0
    0x00000000

    4. Next step is to try reconfigure the fPLL, Could you refer some documentation or steps for fPLL reconfiguration process ?

    fPLL refclk and CLKUSR are directly sourced from stable and free-running oscillators on-board and they seems to be good because everything is working when CvP mode is disabled.

    Regards,

    Piyush.

    • Piyush_Patel's avatar
      Piyush_Patel
      Icon for New Contributor rankNew Contributor
      5 years ago

      Signal tap Write/Read command Captures

      Write command

       Read command

       

      No fPLL lock, so I will continue exploring the fPLL reconfiguration as suggested by Chee Pin.

      Regards,

      Piyush.

      • Piyush_Patel's avatar
        Piyush_Patel
        Icon for New Contributor rankNew Contributor
        5 years ago

        Hi Chee pin and John

        I followed the steps mentioned in section 7.5.2. Fractional PLL Recalibration of ug_arria10_xcvr_phy.pdf

        I implemented the system console command sequence as below :

        # Follow these steps to re calibrate the fPLL:

        # Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0]
        #::ist::write_tcvr_pll_reg 0x000 2

        #Wait for reconfig_waitrequest to be deasserted (logic low) or wait until capability register of PreSICE Avalon memory-mapped interface control0x280[2]=0x0
        #::ist::read_tcvr_pll_reg 0x280

        #To calibrate the fPLL, Read-Modify-Write 0x1 to bit[1] of address 0x100 of the fPLL
        #::ist::write_tcvr_pll_reg 0x100 2

        #Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0]
        #::ist::write_tcvr_pll_reg 0x000 1

        I do get the fPLL lock and SDI output is up and running successfully.

        I really appreciate your suggestions

        Regards,

        Piyush,

        Regards,

        Piyush.