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Piyush_Patel's avatar
Piyush_Patel
Icon for New Contributor rankNew Contributor
5 years ago
Solved

SDI video output not working in CvP mode

We are trying to leverage the arria 10 CvP (Configuration Via Protocol) feature into the current project. So far we have followed the steps as per user guide ug_a10_cvp_prop.pdf As part of the proc...
  • Piyush_Patel's avatar
    Piyush_Patel
    4 years ago

    Hi Chee pin and John

    I followed the steps mentioned in section 7.5.2. Fractional PLL Recalibration of ug_arria10_xcvr_phy.pdf

    I implemented the system console command sequence as below :

    # Follow these steps to re calibrate the fPLL:

    # Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0]
    #::ist::write_tcvr_pll_reg 0x000 2

    #Wait for reconfig_waitrequest to be deasserted (logic low) or wait until capability register of PreSICE Avalon memory-mapped interface control0x280[2]=0x0
    #::ist::read_tcvr_pll_reg 0x280

    #To calibrate the fPLL, Read-Modify-Write 0x1 to bit[1] of address 0x100 of the fPLL
    #::ist::write_tcvr_pll_reg 0x100 2

    #Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0]
    #::ist::write_tcvr_pll_reg 0x000 1

    I do get the fPLL lock and SDI output is up and running successfully.

    I really appreciate your suggestions

    Regards,

    Piyush,

    Regards,

    Piyush.

JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


May I know if you are running the same board when testing the design? Could you share with me your Quartus Project for CvP so that I can further look into the issue?


  • Piyush_Patel's avatar
    Piyush_Patel
    Icon for New Contributor rankNew Contributor
    5 years ago

    Yes, I am running the same board when testing the design. After entering into user mode, only SDI output doesn't work when CvP is enabled and rest of the FPGA logic works fine .

    When building the same project without CvP enabled works just fine including SDI.

    I will share the Quartus project with CvP enabled for your review.

    Thanks

    • Piyush_Patel's avatar
      Piyush_Patel
      Icon for New Contributor rankNew Contributor
      5 years ago

      Please find the attached CvP_SDI_Issue.zip for your review.

      Project was build in Quartus 19.3. Please advice. Let me know if you need any more info.

      • Piyush_Patel's avatar
        Piyush_Patel
        Icon for New Contributor rankNew Contributor
        4 years ago

        Hi John,

        I just wanted to follow up on the SDI project that I shared few days back.

        Please review and see if you can provide any suggestions/workaround.

        Appreciate you support.

        Regards,

        Piyush.