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Piyush_Patel's avatar
Piyush_Patel
Icon for New Contributor rankNew Contributor
5 years ago
Solved

SDI video output not working in CvP mode

We are trying to leverage the arria 10 CvP (Configuration Via Protocol) feature into the current project. So far we have followed the steps as per user guide ug_a10_cvp_prop.pdf As part of the proc...
  • Piyush_Patel's avatar
    Piyush_Patel
    5 years ago

    Hi Chee pin and John

    I followed the steps mentioned in section 7.5.2. Fractional PLL Recalibration of ug_arria10_xcvr_phy.pdf

    I implemented the system console command sequence as below :

    # Follow these steps to re calibrate the fPLL:

    # Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0]
    #::ist::write_tcvr_pll_reg 0x000 2

    #Wait for reconfig_waitrequest to be deasserted (logic low) or wait until capability register of PreSICE Avalon memory-mapped interface control0x280[2]=0x0
    #::ist::read_tcvr_pll_reg 0x280

    #To calibrate the fPLL, Read-Modify-Write 0x1 to bit[1] of address 0x100 of the fPLL
    #::ist::write_tcvr_pll_reg 0x100 2

    #Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0]
    #::ist::write_tcvr_pll_reg 0x000 1

    I do get the fPLL lock and SDI output is up and running successfully.

    I really appreciate your suggestions

    Regards,

    Piyush,

    Regards,

    Piyush.

JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Just would like to confirm if the design already enter user mode when you are checking the SignalTap? Could you help to check why the digitalreset is high?


Have you try to reset the SDI after you enter user mode to see if it is able to recover?


Piyush_Patel's avatar
Piyush_Patel
Icon for New Contributor rankNew Contributor
5 years ago

Hi JohnT,

Thank you for your response.

Yes, Design is already enter into user mode when I am checking the SignalTap.

I think the reason for digital reset is high from PHY reset controller IP is because the PLL lock (input) signal is low from PLL IP.

I tried resetting the SDI after FPGA enters into user mode, it doesn't recover and digital reset remains high with no PLL lock.