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Piyush_Patel's avatar
Piyush_Patel
Icon for New Contributor rankNew Contributor
5 years ago
Solved

SDI video output not working in CvP mode

We are trying to leverage the arria 10 CvP (Configuration Via Protocol) feature into the current project. So far we have followed the steps as per user guide ug_a10_cvp_prop.pdf As part of the proc...
  • Piyush_Patel's avatar
    Piyush_Patel
    4 years ago

    Hi Chee pin and John

    I followed the steps mentioned in section 7.5.2. Fractional PLL Recalibration of ug_arria10_xcvr_phy.pdf

    I implemented the system console command sequence as below :

    # Follow these steps to re calibrate the fPLL:

    # Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[7:0]
    #::ist::write_tcvr_pll_reg 0x000 2

    #Wait for reconfig_waitrequest to be deasserted (logic low) or wait until capability register of PreSICE Avalon memory-mapped interface control0x280[2]=0x0
    #::ist::read_tcvr_pll_reg 0x280

    #To calibrate the fPLL, Read-Modify-Write 0x1 to bit[1] of address 0x100 of the fPLL
    #::ist::write_tcvr_pll_reg 0x100 2

    #Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset address 0x0[7:0]
    #::ist::write_tcvr_pll_reg 0x000 1

    I do get the fPLL lock and SDI output is up and running successfully.

    I really appreciate your suggestions

    Regards,

    Piyush,

    Regards,

    Piyush.

JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


May I know if you have try to reset the SDI IP and also monitor the SDI IP signal using SignalTap?


Piyush_Patel's avatar
Piyush_Patel
Icon for New Contributor rankNew Contributor
5 years ago

Yes, I tried resetting the SDI IP but no luck. The ready status from Transceiver PHY reset controller ramains low (which is why I am not getting the SDI video output).

So currently I am monitoring other signals like PLL locked, cal_busy for PLL and transceiver PHY, just to make sure the calibration is done. I also have to make sure that the transceiver went through correct reset sequence.

I will keep you posted with more information soon.

Do I have to do something specific for transceiver calibration and transceiver reset sequence as far as CvP initialization mode is concern ?

  • Piyush_Patel's avatar
    Piyush_Patel
    Icon for New Contributor rankNew Contributor
    5 years ago

    After CvP initialization is Done, capture SDI PLL and reset transceiver signals in Signal Tap

    1. When SDI is working (Without CvP enabled - programming normal *.sof) tx_ready is high and PLL is locked - see attached capture "Working Condition PLL Locked.JPG" and other signals are also in correct state.

    2.When SDI is not working (CvP Enabled) tx_ready is low and PLL is not locked, digital reset is high from transceiver reset (may be due to missing lock input) - see attached capture "Not Working no PLL lock Digital reset high"

    3. I verifed the PLL input clock (148.5 MHz) using oscilloscope, in fact I am using the same clock as sample clock in signal tap. I also try resetting the reset controller which drives the the pll_powerdown input, still not getting the PLL lock after de assertion of reset- see attached "pll_powerdown active.jpg"

    It seems PLL lock is the issue, However, In all cases busy signal remains low ? does that mean the calibration is successfully done during CvP initialization?

    Any thoughts ?? Thanks.