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AlexR's avatar
AlexR
Icon for New Contributor rankNew Contributor
7 years ago

SDI II IP - TX sync Issue

Hi, In the CycloneV GX project, I configured the SDI II core as follows: bidir, 3G SDI only, transceiver and protocol, CMU, dynamic switching off. I found out that the SDI output in my project is...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Aleksander,

I attached the example from wiki for your reference.

If your design is doing SDI RX -> FIFO - SDI TX, then you need a external VCXO to sync the clock so that the FIFO won't over flow or underflow. Could you please check if the FIFO is overflow or underflow in your case? The output of the VCXO should connect to the TX refclk, and the txcoreclk is suggested to share with TX refclk. Please look at the following document for the implementation of VCXO in other examples.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an668.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-sdi-ii-de.pdf

Regards -SK ​