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HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
5 years ago

sd_threshold setting in Quartus for transceivers

Hi,

For Arria 10 devices, below sd_threshold option can be given in QSF file.

"

For your reference, as per the A10 user guide, in SATA application, the following values are used:

For SR: sd_threshold for SATA = SDLV_4

For LR: sd_threshold for SATA = SDLV_6

"

Can anyone please explain the meaning of these commands & how to apply this for any custom protocol?

Also, whether same option is applicable for Stratix 10?

This question is linked to below question

https://community.intel.com/t5/FPGA-Intellectual-Property/Electrical-IDLE-entry-exit-detection-on-receiver-side-of-the/td-p/660027

With regards,

HPB

2 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi HPB,


    As I understand it, you have some inquiries related to the signal detect threshold settings. As I further look into the user guide and cross check with Quartus Assignment Editor, I understand that the threshold would be dependent on the "Receiver Link Type" assignment in Assignment Editor. You can choose LR or SR for this. There is no direct QSF assignment to set the SDLV values. After the Fitter compilation, you can check the GXB Reports -> Receiver Channel -> "HSSI PMA RX SD" on the Fitter auto-assigned value.

    Please let me know if there is any concern. Thank you.


    Best regards,

    Chee Pin



  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.