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Altera_Forum's avatar
Altera_Forum
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8 years ago

Sata 2.0

Hi, I'm (quite) new about forum. Sorry if my post is not in the correct section. I'm working to design a Sata controller. I'm using a Cyclone V 5CGX. I started to develop a preliminary draft of ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Further question: if in Cyclone V Transceiver Native PHY is set Standard PCS/PMA interface width 20, and consequently FPGA fabric/PCS interface is set automatically to 32, why in the generated wrapper I find

tx_parallel_data : in std_logic_vector(43 downto 0) and

rx_parallel_data : out std_logic_vector(63 downto 0) ?

I should expect 32 bit interface. Which others parameters I need to set to have 32 bit FPGA/PCS interface?

Best regards,

Gabriele