New Contributor
New ContributorHello SooY_Intel,
thank you for your answers.
First question:
No, on our Boards are no MAX10 devices. Just one Cyclone IV-GX each. The MAX6390 is a Power-Supervisor from Maxime. But the main Question is: How do I see if have to reset the RSU-Block or not. The first time when the FPGA is in Factory-Image (just after Power-On) the RSU has to be reset. Thats written in the RSU-Documentation. Anytime later the Factory-Image must not reset the RSU since the FPGA can be configured with the Factory-Image due to an Error. By resetting the RSU we lose the Information about this error. To do so I have do differentiate a Power-On event from any other reconfiguration of the FPGA.
With an external CPU as a supervisor that would be simple. But our external CPU is connected via PCIe and is not running when the devices are configured.
Second question:
OK, I will try both designs with the early pof checking. But the check is only applied on a really small part of the image right?
Third question:
My used documents is UG-31005 from 2019.12.24
The part about read_source is on Page 33.
In Hardware I have seen contents in the register 1 and 2 when the FPGA seems to be in Application for the first time after Power-On. The dokument looks like no information about the Factory-Image is stored. Is that right?
The Reconfiguration_trigger_register has sometimes more than one bit set. Is there any reference like: reconfiguration via RSU-Reconfig leads to value XY or something?
