rst_n port on the pll is not properly connected

Hello,

I am sorry for not updating my case. Actually, I have found an error in my reset generation bloc that makes the reset signal always stuck on '0'. Thus, the synthesis tool, makes his optimisation process by deleting the reset bloc with other design parts. Then it considers that the reset signal of the PLL is not connected which generates this error message.

Thank you for your help.

Best regards,

Lotfi.