Honored Contributor
Honored ContributorHi Kaz,
--- Quote Start --- I have been through dsp projects with/without rounding. The notion of dc unbiased version is relatively new. In most cases I had to please the rf engineer by removing a tiny speckle of dc in the spectrum centred on carrier frequency. --- Quote End --- It ends up being important if you do a lot of complex-valued baseband processing, since the quantization noise spike shown in the slides shows up the in 'middle' of your band. If you were only processed real-valued signals, then the DC channel is probably discarded anyway, so its not as critical. --- Quote Start --- I am however not clear about round() having positive/negative dc as in your slide. If you look at my table above then there is no way I can imagine dc bias as values are symmetrical around zero. However, I do have some doubts about why the stress has moved to convergent case. Any clarification appreciated. --- Quote End --- round() is interesting isn't it. There is no bias if you take all the data and perform a 'mean' on it, but you can see from the figure in the slide that the positive values of the signal have a slight positive bias, while the negative have a slight negative bias, due to the rounding of 0.5 values to the next whole value in magnitude, i.e., 2.5 rounds to 3, and -2.5 rounds to -3. Though, I'm not sure how you'd see this effect in practice. The convergent rounding operation is pretty simple to implement in VHDL, see the attached. Since its so simple, I just 'use it' :) Cheers, Dave
