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I do no special setup of the Marvel Chip, because I also have no datasheet.
The hint with the 90deg phase was the solution. I created a PLL for the 125 MHz signal. The 0-degree frequency goes into the TX_clock of the IP-core.
The 90-degree freqency goes into the PHY GTX clock.
Then sending of a frame succeeds.
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Does this work for non-gigabit speeds? My PHY is running at 100Mb and I am confused whether the clock needs to be delayed 90deg or a fixed amount of time. Big difference when switching between 125, 25, and 2.5MHz. Ideally I would like the ethernet port to handle all three link speeds.
I am trying to get RGMII working on the arria ii devkit, and maybe this is my problem. I've also seen discussion of writing to a register in the PHY to let it handle the clock skew, but I have not seen and code to actually do this.
Any insight into this matter will be appreciated.
Honored Contributor
