Honored ContributorHi all,
Iam a beginner to altera FPGA ,Iam using the Remote system update IP core in my project,there's no information on it in the quartusll handbook ,so can any please provide me the link to download the datasheet of Remote system update ip core Thanks in advance Regards Gowtham
Honored ContributorA link is present in the Quartus MegaWizard documentation page.
Honored ContributorI will admit the remote system upgrade can be a bit daunting at first. Which FPGA device are you using?
JakeHonored Contributor@jakobjones
iam using Cyclone lll This remote update controller is used only for loading the new configuration from the EPCS flash,am i right.? And for writing the new configuration image to the EPCS without the help of Quartus2 i have to go for EPCS flash controller core, whose pins are mapped to the 4 dedicated pins, which are used to connect the EPCS configuration memory is it right..? Please verify my doubtsHonored ContributorCorrect. The EPCS controller basically provides you with read/write access to the serial flash device (EPCS). Obviously you need this if you plan to dynamically update the contents of the EPCS via the NIOS processor.
The remote update controller is a combination of firmware and hard silicon within the FPGA that allows you to dynamically reload the FPGA with a new firmware image and provides sufficient circuitry to recover from a failed configuration attempt (like if your image was bad). JakeHonored ContributorAnd i have a doubt like whether this remote update controller core supports for both serial and parallel EPCS flash memory
if it supports for both, is this core separate for serial and parallel EPCS memoriesHonored ContributorTo be honest, I would need to read the user's guide for the Cyclone III. For Stratix II/IIGX, the core supports both serial and parallel configuration schemes. However, a slight correction to your previous statement; EPCS devices are serial devices only. Also, you have to configure the core for either serial or parallel. It cannot do both at the same time.
JakeHonored ContributorOk clear..
iam writing to the EPCS flash memory using a EPCS flash controller core through nios2 without the help of Quartus2. but to write to the EPCS flash memory we need to know the memory map of it.(ie no of blocks in the flash and address range of each block).but the configuration handbook doesn't give the information about that.is there any other document which describes about that and were do i get that details.Honored ContributorHere you go.
http://www.altera.com/literature/hb/cfg/cyc_c51014.pdf Look at page 4-10 Jake
