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Altera_Forum
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13 years ago

Reg:SDI IP clocks synchronization issue

Hi All,

SDI megacore IP has 3 clocks: tx_pclk, tx_serial_refclk and gxb2_cal_clk. If we see the ug_sdi Figure 3–3. Transmitter Clocking Scheme block diagram it has been showed that three clocks are going to different blocks. Is there any relationship among these clocks in terms of pahse/source ?

Since in my requirement, video clock is from different source {which have been connected to gpio pin of arria ii gx, not allowing the fitter, pll to derive remaining clocks};please find attachment . So if i use the video clock as pclk and Remaining clocks{tx_serial_refclk and gxb2_cal_clk} from pll of different source then video is not getting lock, I mean, can not see the video on display. I hope there may be relationship among the clocks.

If any relationship/method to route the GPIO input to the PLL then please let me know.

Sorry for my poor English.

Thanks,

Shivaji M.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thanks for reply.

    All the dedicated clocks in that bank are connected to other interface clocks of processor. so we connected at the board design pahse to the gpio of fpga. and worked for sd and hd alone, so its worked fine{plck,refclk directly connected to video clock coming form the GPIO}.

    Now we have requirement for triple rate sdi, for that we need:74.25MHz-pclk and 148.5MHz reference clock.

    it is not possible to generate the two separate video clocks from the processor at the running time. it will give only one clock at a time in one video standard display.

    Is there relation for all the cloks : pclk, reference clock and gxb2_cal _clk ? or we can feed the clocks from different sources{we tried this one but its not satisfied us}.

    please gives us any hit/suggestion so that we can cater this synchronization issue. also some thing reference for the same is well and good.

    Thanks,

    Shivaji M