Reg:SDI IP clocks synchronization issue

Thanks for reply.

All the dedicated clocks in that bank are connected to other interface clocks of processor. so we connected at the board design pahse to the gpio of fpga. and worked for sd and hd alone, so its worked fine{plck,refclk directly connected to video clock coming form the GPIO}.

Now we have requirement for triple rate sdi, for that we need:74.25MHz-pclk and 148.5MHz reference clock.

it is not possible to generate the two separate video clocks from the processor at the running time. it will give only one clock at a time in one video standard display.

Is there relation for all the cloks : pclk, reference clock and gxb2_cal _clk ? or we can feed the clocks from different sources{we tried this one but its not satisfied us}.

please gives us any hit/suggestion so that we can cater this synchronization issue. also some thing reference for the same is well and good.

Thanks,

Shivaji M