Regenerating PCIe IP Core Destroys Functionality

Thanks for the replies. It looks like there are indeed changes starting in 10.1 that affect the reset logic/ports, but even with this cleaned up, I cannot get a link up after regenerating in 10.1

With the latest version of Qsys, not all options in the PCIe IP core are available (max lanes, may payload, etc.).

I removed some termination settings, but still no luck.

In the end, I kept the 9.1/10.0 PCIe IP core design, and manually modified the parameters in altpcierd_example_app_chaining and top_core. They are not all explicity defined, but by going through the UG, you can figure out what the settings and parameters map to.

Hopefully in 12.0, this design will be updated AND the BFM will be included.