Reference Design RP to EP?

Question

Dear Community,
I am looking for a small, well-explained example or tutorial for a very simple data transfer between a PCIe SOC HIP Root Port and an PCIe HIP endpoint.

I worked through this: https://rocketboards.org/foswiki/Projects/PCIeRootPort
and that: https://rocketboards.org/foswiki/Projects/PCIeRootPortWithMSI
But there are files missing and errors occur and the projects are not well enough documented to find the errors without too much effort.

My Dev Kits are:

Root Port: Cyclone V SoC Development Kit (5CSXFC6)
Endpoint: 5CGTFD9EF35C7, https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-gt.html

Best Regards

eberlazare_i_intel · Answer

Hi,Can you check from your side if you can access the full design here:https://releases.rocketboards.org/release/2015.10/pcie-ed/hw/

eberlazare_i_intel · Answer

Hi,Do you have any update?

zarquin · Answer

Dear EBERLAZARE,
I can access the full design files from your link above.
But these seem to be the hardware files from the Rocket PCIe RootPort with MSI example I already have. (?)
The problem with the Rocket examples is that the:

PCIe RootPort example is missing the hardware files
PCIe RootPort with MSI example is missing the SD-image

I tried to combine the examples but without success.

Best regards

eberlazare_i_intel · Answer

Hi,Unfortunately, you may have to build the Uboot and kernel after compiling the GHRD in Quartus, as demonstrate at the bottom of the page.

eberlazare_i_intel · Answer

Hi,Do you have any further questions?

Forum Discussion

Reference Design RP to EP?

5 Replies

Recent Discussions

PCIe Enumeration Failure for CXL IP

Can't generate F-Tile Ethernet Hard IP Design Example

Agilex 7 slew rate reconfiguration

Constraints not being picked for DCFIFO

Cyclone 10 GX IBIS-AMI models