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1) Is it possible to provide the source reference clock to the IO transceivers through some other port (like the LVDS clock inputs)?
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You'll have to check the schematic. If you can access a CLKIN pin rather than a REFCLK pin, you can use a PLL to also provide the transceiver reference clock.
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2) Can it be guaranteed that all the 15 received channels would exactly align in phase? Since the channels are source synchronous, the data received from all channels needs to be phase aligned to reconstruct the correct word.
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No. All the SERDES lane parallel output data will have the bits packed into words in sequence, but the start bit can vary between channels. You will need to use a pattern in the received data to align words. Can you control the data pattern?
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3) Can I rely on the CDR function of the IO transceivers to recover the clock, without supplying any reference clock? If I do so, is there any guarantee that all 15 channels would be aligned in phase (see (2) above)?
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If your reference clock can be routed to the board, then use a PLL, and then use the PLL output as the REFCLK. If you cannot access a CLKIN pin, but there is a 100MHz reference clock on the board, use a PLL to create a reference clock with a matching lane rate and that should be sufficient to get the CDR to start in lock-to-reference mode, and then transition to lock-to-data mode.
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Anybody sharing their experience or links to some literature would be highly appreciated.
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Read the transceiver docs at the top of this page
https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html PS. I'm using the Stratix IV GX Development kits, so am familiar with the IP you need to use :)
Cheers,
Dave
Honored Contributor
