Receive Transceiver clock recovery problem without loopback

Problem solved!

Since the example design provided by Terasic was for the development kit, I had to change the pin assignments and clocks used to make it work with the DE4 (I did this a long time ago). In this process, the pin for the clk2_p clock was set to a 2.5V pin by default, whereas in the design it was intended to be used in LVDS mode.

I changed it back to LVDS and now the LTD seems to behave more normally: It actually doesn't lock when the cables aren't connected properly (the LED indicating successful locking flickers).

I imagine it worked in the loopback case because the transmitter and receiver had the exact same clock, so it wasn't a problem. But in the real case I guess that some ppm differences between the clocks made the CDR unit fail.

I get another problem now though. In a simple design all 4 channels work well. But when I use a bigger design with some other transceivers, 3 of the channels work fine, channel# 0 properly sends the data, but does not receive anything (al 0's). I know it sends data properly because if I interface the big design with the small one, the small one actually receives data. Maybe it's a conflict between transceivers in the big one... ?!?!

But this is not related to this topic anymore, hopefully I will find a solution soon...

Thanks for your help Dave!