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>> However, none of the REFCLK signals from the transceivers route via the HSMC connector
What do you mean?
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See page 46 of the HSMC specification:
http://www.altera.com/literature/ds/hsmc_spec.pdf Connector pins 1 to 32 are defined as transceiver lanes, but there is no assignment for a transceiver REFCLK clock.
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I think that clk2_p/n (figure 2.3 in the manual) is the clock that the design sees as the pair hsmb_clk_in_p2 and hsmb_clk_in_n2, which is then used as a refclk further in the code by the CDR (the code is available on the website too).
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That is possible, however, it would be a function of the DE4 board clock distribution. You'd want to check that documentation to see what clocks on the HSMC route to FPGA pins that can be used as REFCLKs.
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What I did now is that I connected clk2_p/n (figure 2.3) from one board into the SMA_clk_p/n of the second board, such that the clk2_p/n of the second board is the same as the one from the first board.
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That sounds reasonable.
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I am not sure if the mux that is pictured would create problems though (like adding a delay to the other clock),
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The delay should not matter. The logic levels of the clocks will. You'll need to see whether things are AC-coupled, whether they require termination, etc.
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It doesn't work though... with this configuration there is no data sent/received by the second board. Either my connections are not what they should be, or the cables I am using aren't doing the job.
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Plug the cable with the clock into a scope and look at it. Use an oscilloscope to probe for the clocks around the place. Implement the clock counter logic I told you I use, and then count clocks. You can send a lower frequency clock around if you are concerned the cables aren't great; once you get things working, increase the clock rate and see if there are issues.
Cheers,
Dave
Honored Contributor
