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This is going to be my next step. I was going to try this this morning but then I lost my motivation when I thought that there would be noise in the SMA connectors etc... so it was probably not gonna work...
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SMA connectors work up to much higher frequencies than the reference clocks. It would be the board layout that could potentially cause issues. However, the Terasic boards are well designed, so you should be ok.
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I am using the "SFP HSMC loopback demo" as a basis for the design. My board is a DE4 with Stratix IV, connected to an SFP HSMC daughter card through HSMC.
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This one?
http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=71&no=342 There are clock input and output SMAs. You should be able to use those.
However, none of the REFCLK signals from the transceivers route via the HSMC connector, so you'll have to see if Quartus will let you use an LVDS clock pin. It should, worst-case you might have to use a general-purpose PLL (ALT_PLL) and then route the PLL output to the transceiver block as the reference clock.
Cheers,
Dave
Honored Contributor
