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Those two signals never get asserted, so i assume there is no error. The 62.5 ppm does not help either.
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I have seen discussions on this group regarding the lock indication signals not really being that meaningful ...
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Could it be that the frequency of the clock on the second board is not EXACTLY the one one the first board, so that it expects arriving data with a frequency derived from a multiple of a 49.5Mhz clock, while the arriving data was generated with a clock with a frequency that is a multiple of a 50.3MHz clock?
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Can you test your theory? Can you get the first board to generate a clock that you then use on the second board as the reference clock?
For my testing, I am using two Stratix IV GX development kits, I have the first send its 156.25MHz reference clock to the second, and then both are operating coherently. I have not tested whether lock-to-data works between two boards with independent oscillators, since this does not reflect what I will be implementing; an ADC-to-FPGA interface.
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This would explain why the CDR works only in a loopback setting. But if this is the case, isn't there a building block in the receiver data path that compensates for this?
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"Lock-to-data" should lock the receive CDR to that of the incoming data.
Here's what I do to check the frequencies of all the clocks;
1) I have an SOPC system with control registers slaves. That system is clocked at 100MHz.
2) I have a block of slave registers that are clock counters.
The clock counters block is enabled by my Avalon-MM master writing to a control register to enable the counters, and then writing again to disable counters. I use Tcl and enable the counters for about 1 second.
The counters count; the system clock (eg., ideally a count of 100M clocks), and all of my external clocks; the external GXB refclk 156.25MHz nominal, and the receiver channel CDR recovered clocks. I then assume my 100MHz is exactly 100MHz, and use Tcl math to calculate the frequencies. In another system, I use an external GPS 1pps tick to get more accurate estimates.
You should create something similar. When you are in LTR mode, your CDR clock count should match that of the reference on the receiver board. When you are in LTD mode, your CDR clock count should match that of the transmitter board.
If your clock counts do not, then the LTD mode is not working properly ... possibly due to too great a mismatch between reference frequencies.
Cheers,
Dave
Honored Contributor
