Honored Contributor
Honored Contributor>> I have launched a new compilation with 62.5 ppm for the threshold that makes the transition between LTR and LTD. I have also added rx_phase_comp_fifo_error and tx_phase_comp_fifo_error ports to see if an error occurs there.
Those two signals never get asserted, so i assume there is no error. The 62.5 ppm does not help either. Could it be that the frequency of the clock on the second board is not EXACTLY the one one the first board, so that it expects arriving data with a frequency derived from a multiple of a 49.5Mhz clock, while the arriving data was generated with a clock with a frequency that is a multiple of a 50.3MHz clock? This would explain why the CDR works only in a loopback setting. But if this is the case, isn't there a building block in the receiver data path that compensates for this?
