Honored Contributor
Honored ContributorThanks for the reply!
I have read some documentation on what you're mentioning. In my design I am not using the rx_locktorefclk nor the rx_locktodata ports, so I think it is in auto mode: First LTR, then it switches to LTD. I am using rx_freqlocked later to check for proper locking, so I think the LTR to LTD transition is properly done. Maybe I could try lowering the PPM (right now it's at +/-1000), or I could start from LTD right away. Also, apparently there's a different reset sequence depending on which mode is used, maybe I only support the one for LTR, so that even if it's in auto mode it doesn't do the LTD properly, except when the reference clocks are the same (in case of a loopback). I'll try this as soon as I get to work later today, and let you know how it goes. The other track I was pursuing was with some rate matching business, but I am not sure how to set this up and edit it in Altera's transceiver functions, I only see some rate_match parameters with constants that I don't understand in the generated megawizard functions... Edit: I have launched a new compilation with 62.5 ppm for the threshold that makes the transition between LTR and LTD. I have also added rx_phase_comp_fifo_error and tx_phase_comp_fifo_error ports to see if an error occurs there. I am a little confused about the functioning of the LTD though, it seems like I always end up switching to LTD and having an asserted rx_freqlocked even when no cable is plugged in (so only garbage data is received), isn't it supposed to lock only when good data is received?
