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I am working on a high speed optical fiber link between two FPGAs. Now the design seems to work perfectly in a loopback setting.
But when I connect two boards together, download the exact same designs on the two boards and analyze the received data with signaltap, I get something that looks like the right stream of bits but with what seems to be a messed up clock (for example every now and then there would be two 1's in a row when there should be only one of them).
I am stunned that clock recovery works fine in a loopback but not in a real setting. Has anyone seen this kind of issue before? any pointers to what could be the issue?
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Are you running the receiver in Lock-to-Reference (LTR) mode, or Lock-to-Data (LTD) mode, or Auto?
If you have the receiver in LTR mode, then it will work in loopback, since the reference clock is identical. For a board-to-board link, you need to use LTD. I find you need to use LTD even if the two boards are phase-locked to the same reference. I suspect its so that the CDR PLL can lock to the 'center' of the data eye pattern.
Cheers,
Dave
Honored Contributor
