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Altera_Forum
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9 years ago

Real time FIR filtering MAX 10 FPGA Development Board

Hi, I am working at implementing a bandpass FIR filter on MAX 10 FPGA development kit. So, I am taking a signal input from the SMA connector into the ADC (1Msps, allowed input clock levels 2, 1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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What does your ADC say about its digital output (you said it gives 1Msps) but what clock does it give you. Remember ADC may have its own internal clock but what matters to you is the clock rate given to you and normally it is same as data rate i.e. 1MHz.

If you have DDR interface it will be 0.5MHz to give you 1Msps

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Kindly have a look