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Honored Contributor
Honored ContributorReal time FIR filtering MAX 10 FPGA Development Board
Hi, I am working at implementing a bandpass FIR filter on MAX 10 FPGA development kit. So, I am taking a signal input from the SMA connector into the ADC (1Msps, allowed input clock levels 2, 1...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- You must sample your data at 1MHz at whatever clock you use (e.g. use clock enable) --- Quote End --- Could you please elaborate? Please have a look at the attachment. According to me its the limitation with allowed values in the ADC
