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Altera_Forum
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9 years ago

Real time FIR filtering MAX 10 FPGA Development Board

Hi, I am working at implementing a bandpass FIR filter on MAX 10 FPGA development kit. So, I am taking a signal input from the SMA connector into the ADC (1Msps, allowed input clock levels 2, 1...
Altera_Forum's avatar
Altera_Forum
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9 years ago

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The maximum as per data sheet is 1 Msps. The Qsys Modular ADC gives the mentioned clock rates.

How can I down sample ? Could you point me to some resources?

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if your sample rate is 1Msps indeed you have no problem and you don't need downsampling. then your p/s convert will have sample rate of 1Msps at its input, 24 Mbps for DAC.

You must sample your data at 1MHz at whatever clock you use (e.g. use clock enable)