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Altera_Forum
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9 years ago

Real time FIR filtering MAX 10 FPGA Development Board

Hi, I am working at implementing a bandpass FIR filter on MAX 10 FPGA development kit. So, I am taking a signal input from the SMA connector into the ADC (1Msps, allowed input clock levels 2, 1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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first you say 1Msps but various clock rates. So I guess your wanted sampling is 1Msps. This means(to me)you are oversampling by 2 f your ADC clock is 2

can't you downsample from 2 to 1 then DAC will be at 24Mhz

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The maximum sampling rate as per data sheet is 1 Msps. Actually I've tried that, the Qsys Modular ADC gives the fixed clock rates even with different sampling rates. So, 2MHz is the lowest I can go

Is there a way around?